Self-aligned gate tie-down contacts with selective etch stop liner

ABSTRACT

A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

BACKGROUND

Technical Field

The present invention relates to semiconductor processing, and moreparticularly to a gate tie-down structure that permits gate contacts inactive areas and reduces shorts between adjacent contacts and gateconductors.

Description of the Related Art

In conventional complementary metal oxide semiconductor (CMOS)processing, gate contacts are formed over shallow trench isolation (STI)regions. Gate contacts connect a gate line to upper metal layers indevice designs. In many instances, providing the gate contacts in STIregions can result in a large amount of chip area being lost.

Gate tie-down structures or regions provide a connection between thegate contact and a source/drain (S/D) region contact. The formation of agate tie-down structure may result in shorts between a silicide regionof the S/D region or with conductive material of an adjacent gate. Thisis due, in part, to the small margins of dielectric materials betweenthese structures and the close proximity of the conductive bodies.

SUMMARY

A method for forming a gate tie-down includes exposing an active area byetching dielectric material on adjacent sides of a gate structure toopen up trench contact openings; forming trench contacts in the trenchcontact openings and forming an etch stop layer on the trench contactsand on spacers of gate structures adjacent to the trench contacts. Aninterlevel dielectric (ILD) is deposited to fill over the etch stoplayer in the trench contact openings and over the gate structuresadjacent to the trench contacts. The ILD and the etch stop layer on oneside of the gate structure are opened up to provide an exposed etch stoplayer portion. The gate structure is recessed to remove a cap layer,recess one spacer and expose a gate conductor. The exposed etch stoplayer portion is removed. A conductive material is deposited to providea self-aligned contact down to the trench contact on the one side of thegate structure, to form a gate contact down to the gate conductor and toform a horizontal connection within the ILD over the active area betweenthe gate conductor and the self-aligned contact.

Another method for forming a gate tie-down includes exposing an activearea by etching dielectric material on adjacent sides of a gatestructure to open up trench contact openings; depositing a firstconductive material in the trench contact openings; recessing the firstconductive material to form trench contacts in the trench contactopenings; conformally depositing an etch stop layer on the dielectricmaterial, on the trench contacts and on spacers of gate structuresadjacent to the trench contacts; forming a planarizing material over theetch stop layer; planarizing to remove the planarizing material and theetch stop layer from a top surface; removing the planarizing materialfrom etch stop portions formed on the trench contacts; depositing aninterlevel dielectric (ILD) to fill over the etch stop portions and overthe gate structures adjacent to the trench contacts; opening up the ILDand the etch stop portion on one side of the gate structure to providean exposed etch stop layer portion; recessing the gate structure toremove a cap layer, recess one spacer and expose a gate conductor;removing the exposed etch stop layer portion; and depositing a secondconductive material to provide a self-aligned contact down to the trenchcontact on the one side of the gate structure, to form a gate contactdown to the gate conductor and to form a horizontal connection withinthe ILD over the active area between the gate conductor and theself-aligned contact.

A gate tie-down structure includes a gate structure including a gateconductor and gate spacers, trench contacts formed on sides of the gatestructure and an etch stop layer portion formed on a gate spacer on oneside of the gate structure and over the trench contact on the one sideof the gate structure. A first interlevel dielectric (ILD) is configuredto bury the gate structure, and a second interlevel dielectric (ILD) hasa thickness and is formed on the first ILD and over the etch stop layerportion. A self-aligned contact connects to the trench contact on theother side of the gate structure. A gate contact is connected to thegate conductor. A horizontal connection within the thickness of thesecond ILD is formed over an active area and connects the gate conductorand the self-aligned contact over a gate spacer formed on the other sideof the gate structure.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a semiconductor device having gatestructures formed in an interlevel dielectric (ILD) in accordance withthe present principles;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1having trench contact openings formed adjacent to a gate structure toexpose an active area in accordance with the present principles;

FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2showing a conductive material formed in the trench openings inaccordance with the present principles;

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3showing the conductive material planarized in accordance with thepresent principles;

FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4showing the conductive material recessed to form trench contacts inaccordance with the present principles;

FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5showing an etch stop layer conformally deposited in accordance with thepresent principles;

FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6showing a planarizing material formed over the etch stop layer inaccordance with the present principles;

FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7showing the planarizing material and the etch stop layer planarized inaccordance with the present principles;

FIG. 9 is a cross-sectional view of the semiconductor device of FIG. 8showing the planarizing material removed from etch stop layer portionsin accordance with the present principles;

FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9showing a top ILD formed on the etch stop layer portions and over thegate structures in accordance with the present principles;

FIG. 11 is a cross-sectional view of the semiconductor device of FIG. 10showing an open etch of the top ILD and the formation of a self-alignedcontact opening in accordance with the present principles;

FIG. 12 is a cross-sectional view of the semiconductor device of FIG. 11showing an etch of a gate contact opening in accordance with the presentprinciples;

FIG. 13 is a cross-sectional view of the semiconductor device of FIG. 12showing an etch stop portion removed in accordance with the presentprinciples;

FIG. 14 is a cross-sectional view of the semiconductor device of FIG. 13showing a conductive material deposition, and the conductive materialand the top ILD planarized to form a gate tie-down structure with a gatecontact, a connection (in the top ILD) and self-aligned contact inaccordance with the present principles; and

FIG. 15 is a block/flow diagram showing methods for forming a gatetie-down in accordance with the present principles.

DETAILED DESCRIPTION

In accordance with the present principles, a gate tie-down structure andmethods for fabrication are provided. The gate tie-down provides a gatecontact (CB) that is able to short against a self-aligned contact (CA)without shorting against a trench silicide (TS) contact. The gatecontact provides a connection to a gate conductor (PC) of a gatestructure employed in a transistor device. The gate conductor in someinstances may be connected to a source or drain region. This is referredto as a gate tie-down. Gate tie-downs in accordance with the presentprinciples may be provided over active regions without suffering fromthe shorting issues of conventional structures.

The present principles provide methods and structures for forminggate-tie-downs with an etch stop layer, e.g., high-k dielectric, toencapsulate source/drain contacts. This etch stop layer preventsbreakthrough into adjacent gate conductors. In addition, the gatetie-downs include a gate contact that is self-aligned to a source/draincontact. The tie-down structure provides a gate contact that can “fly”over the source/drain contact making the design more compact savingprecious chip area. For example, the gate tie-down structure can beallowed on or over active areas (AA). The gate contact structure enablesthe gate contact to fly over a source/drain contact to reduce a layoutfootprint. The gate tie-down structure may be employed in memorydevices, e.g., static random access memory (SRAM), processors, or otherchip devices.

It is to be understood that the present invention will be described interms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps may be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments may be included in an integrated circuit orintegrated circuit design. A design for an integrated circuit chip maybe created in a graphical computer programming language, and stored in acomputer storage medium (such as a disk, tape, physical hard drive, orvirtual hard drive such as in a storage access network). If the designerdoes not fabricate chips or the photolithographic masks used tofabricate chips, the designer may transmit the resulting design byphysical means (e.g., by providing a copy of the storage medium storingthe design) or electronically (e.g., through the Internet) to suchentities, directly or indirectly. The stored design is then convertedinto the appropriate format (e.g., GDSII) for the fabrication ofphotolithographic masks, which typically include multiple copies of thechip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a cross-sectional view of apartially fabricated semiconductor device 10 is shown in accordance withthe present principles. The device 10 is formed on a substrate 12, whichmay include any suitable substrate materials, such as Si, SiGe, SiC,III-V etc. Gate structures 18 are formed on the substrate 12 and mayinclude source/drain (S/D) regions 26 adjacent to the gate structures18. The gate structures 18 may include a gate dielectric 28 (e.g., anoxide) and a gate conductor 22, which may include a metal, dopedpolysilicon or other suitable gate conductor material. Spacers 20 areformed on sidewalls of the gate conductor 22, and a cap layer 24 isformed over the gate conductor 22. The spacers 20 and the cap 24 mayinclude a silicon nitride material, although other dielectric materialsmay be employed. Gate structures 18 are buried in an interleveldielectric (ILD) material 14, such as an oxide. Another ILD 16 is formedover the gate structures 18 and on the first ILD 14. The ILD 16 may alsoinclude an oxide.

Referring to FIG. 2, recesses or trenches 30 are etched through the ILD14 and ILD 16 for selected gate structures 18. The recesses 30 areformed to gain access to the S/D regions 26 adjacent to the spacers 20of the gate structures 18. The recesses 30 are formed by performing alithographic patterning process followed by an etch process to open therecesses 30 and expose the S/D regions 26. The etch process may includea reactive ion etch (RIE) selective to the cap layer 24 and spacers 20(e.g., nitride material) of the gate structures 18. The recesses 30allow for a self-aligned contact to be provided as will be described.

Referring to FIG. 3, a deposition process is performed to fill trenches30 between spacers 20 of adjacent gate structures 18 and over the ILD 16with a conductive material 32. The deposition process may include achemical vapor deposition (CVD) process although other depositionprocesses may be employed. The conductive material 32 may include W,although other metals may be employed, e.g., Al, Cu, Ag, etc. Theconductive material 32 connects to the S/D regions 26. The conductivematerial 32 preferably includes the same materials as the gateconductors 22.

Referring to FIG. 4, a planarization process is performed to planarize atop surface of the device 10 to remove excess conductive material 32.The planarization process may include a chemical mechanical polish (CMP)process. The planarization process removes the ILD 16 down to the caplayer 24.

Referring to FIG. 5, a recess process is performed to recess theconductive material 32 to a position along the spacers 20. The recessprocess may include a RIE process that selectively removes theconductive material 32 relative to the ILD 14, the spacers 20 and thecap layer 24. In one embodiment, the ILD 14 includes oxide, and thespacers 20 and cap layer 24 include nitride. Recessing the conductivematerial 32 forms trench silicide (TS) contacts 36, which contact theS/D regions 26 (also called S/D contacts). The recess process formsrecesses 34.

Referring to FIG. 6, an etch stop layer 38 is conformally formed on theILD 14 and in the recesses 34 on the cap layer 24 and over the spacers20 of the gate structure 18. The etch stop layer 38 may include a highselective etch stop layer (HS-ESL) and may include a high-k dielectricmaterial, such as e.g., HfO₂, AlO₂, Ta₂O₅, etc., although othermaterials may be employed. The etch stop layer 38 preferably includes aselectivity greater than that of the cap layer 24 and the spacers 20(e.g., greater than silicon nitride in one embodiment).

Referring to FIG. 7, a spin-on or deposition process is performed tofill recesses 34 on the etch stop layer 38 on the gate structures 18with a planarizing material 40. In one embodiment, the material 40includes a spin-on organic dielectric material, such as, e.g.,polyimide, polynorbornenes, benzocyclobutene or similar spin-on organicdielectric material.

Referring to FIG. 8, a planarization process is performed to planarize atop surface of the device 10 to remove excess material 40 and etch stoplayer 38 down to the cap layer 24. The planarization process may includea CMP process.

Referring to FIG. 9, a selective etch process may be performed to removethe material 40 from the etch stop layer 38 in the recesses 34. The etchprocess may include RIE, which is selective to the material of the caplayer 24, the ILD 14 and the etch stop layer 38.

Referring to FIG. 10, another ILD 42 is deposited on the device 10. TheILD 42 may include an oxide although other dielectric materials may beemployed. The ILD 42 fills the recesses 34 and covers the cap layer 24and the ILD 14.

Referring to FIG. 11, a lithographic patterning process is employed toform an opening 44 through the ILD 42. Once patterned the ILD 42 isetched to remove material from opening 44 and within region 52. The etchprocess selectively removes the ILD material (e.g., oxide) with respectto the etch stop layer 38 and the cap layer 24. The etch process mayinclude a RIE.

Referring to FIG. 12, another lithographic patterning process isemployed to open the cap layer 24 to expose the gate conductor 22 andrecess one spacer 20. The etch process removes the cap layer 24 andexposes a portion 48 of the other spacer 20 to form region 50. A portion46 of the etch stop layer 38 may be thinned by the etching process. Theetch process selectively removes the cap layer 24, spacer 20 relative tothe ILD material 42 (e.g., oxide) and the etch stop layer 38. The etchprocess may include a directional RIE.

Referring to FIG. 13, another lithographic patterning process isemployed to remove the exposed portion of the etch stop layer 38selectively to the ILD 42, gate conductor 22 and spacers 20 (e.g.,selective to oxide and nitride). With the etch stop layer 38 removed, acontact opening 54 is made for a self-aligned contact (CA) down to theTS contact 36. In addition, a contact opening 56 is made for a gatecontact (CB).

Referring to FIG. 14, a deposition process is performed to deposit aconductive material 60 to form gate contacts 64 (CB), self-alignedcontacts 62 (CA), and a gate tie-down structure 66. The conductivematerial 60 preferably includes a same material as employed for TScontacts 36 and gate conductor 22. In one embodiment, the conductivematerial 60 includes W, although other metals may be employed. Theconductive material 60 and the ILD 42 are planarized to recess thematerial 60 such that a portion of the conductive material 60 forms aconnection 74 between the gate contact 64 and the contact 62 (thatconnects to the TS contact 36). The connection 74 is buried within athickness of the ILD 42.

In accordance with the present principles, the gate tie-down structure66 provides a self-aligned gate contact (CB) 64 that shorts directly tocontact 62 (CA) and not directly to the TS contact 36. A spacer 68 alongwith the etch stop layer 38 prevents shorts between the adjacent contact36 and the gate conductor 22. A spacer 70 prevents shorts between theadjacent contact 36 and the gate conductor 22 (shorts in this regionoccurred in conventional structures). A spacer 72 provides a dielectricbarrier that prevents direct shorting between the gate contact 64 andthe TS contact 36. In addition, the gate contact 64 is self-aligned withthe self-aligned contact 36. The gate contact 64 is made within theactive region (over S/D regions 26). This reduces the layout footprintof the device 10. In other words, a horizontal connection 74 is madedirectly between the gate contact 64 and the self-aligned contact 62using vertical space provided by the ILD 42. This connection 74 is madewithout having to use layout area, which would normally be consumed byplacing the connections over an STI region outside of the S/D regions(active area). The present principles may be implemented in 7 nmtechnology, although other technology sizes (larger or smaller maybenefit from the present principles).

Referring to FIG. 15, methods for forming a gate tie-down are shown inaccordance with the present principles. In some alternativeimplementations, the functions noted in the blocks may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

In block 102, after gate structures and source and drain (S/D) regionsare formed, an active area is exposed by etching dielectric material onadjacent sides of a gate structure to open up trench contact openings.In block 104, a conductive material is deposited in the trench contactopenings. In block 106, the conductive material is recessed to formtrench contacts in the trench contact openings. In block 108, an etchstop layer is conformally deposited on the dielectric material, on thetrench contacts and on spacers of gate structures adjacent to the trenchcontacts. The etch stop layer may include a high-k dielectric material.

In block 110, a planarizing material is optionally formed over the etchstop layer. The planarizing material may include a spun on organicmaterial. In block 112, planarizing material and the etch stop layer areplanarized to remove them from a top surface. In block 114, theplanarizing material is removed from etch stop portions formed on thetrench contacts.

In block 116, an interlevel dielectric (ILD) is deposited to fill overthe etch stop portions and over the gate structures adjacent to thetrench contacts. In block 118, the ILD and the etch stop portion areopened up on one side of the gate structure to provide an exposed etchstop layer portion. In block 120, the gate structure is recessed toremove a cap layer, recess one spacer and expose a gate conductor. Therecessed spacer remains to permit contact between a self-aligned contactand a gate contact (which will be formed) and to prevent contact betweenthe trench contact and the gate conductor.

In block 122, the exposed etch stop layer portion is removed. In block124, another conductive material is deposited to provide a self-alignedcontact down to the trench contact on the one side of the gatestructure, to form a gate contact down to the gate conductor and to forma horizontal connection within the ILD over the active area between thegate conductor and the self-aligned contact. The etch stop portionopposite the one side of the gate structure remains with a correspondingspacer of the gate structure to prevent shorts between one of the trenchcontacts and the gate conductor. The exposed etch stop layer portionprevents erosion of a spacer of an adjacent gate structure to preventshorts between one of the trench contacts and a gate conductor of anadjacent gate structure. The ILD includes a thickness above the caplayer of the gate structures, and the horizontal connection between thegate conductor and the self-aligned contact is formed within the ILDthickness. In block 126, processing continues to complete the device.

Having described preferred embodiments for gate tie-down with a highlyselective etch stop liner (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope of the invention asoutlined by the appended claims. Having thus described aspects of theinvention, with the details and particularity required by the patentlaws, what is claimed and desired protected by Letters Patent is setforth in the appended claims.

1. A gate tie-down structure, comprising: a gate structure including agate conductor and gate spacers; trench contacts formed on sides of thegate structure; an etch stop layer portion formed on a gate spacer onone side of the gate structure and over the trench contact on the oneside of the gate structure; a first interlevel dielectric (ILD)configured to bury the gate structure; a second interlevel dielectric(ILD) having a thickness and being formed on the first ILD and over theetch stop layer portion; a self-aligned contact connecting to the trenchcontact on the other side of the gate structure; a gate contactconnected to the gate conductor; and a horizontal connection within thethickness of the second ILD formed over an active area and connectingthe gate conductor and the self-aligned contact over a gate spacerformed on the other side of the gate structure.
 2. The structure asrecited in claim 1, wherein the etch stop layer portion prevents shortsbetween one of the trench contacts and the gate conductor.
 3. Thestructure as recited in claim 1, wherein a spacer of an adjacent gatestructure remains intact throughout processing due to a removed etchstop layer portion to prevent shorts between one of the trench contactsand a gate conductor of an adjacent gate structure.
 4. The structure asrecited in claim 1, wherein the second ILD includes a thickness above acap layer of adjacent gate structures, and the horizontal connectionbetween the gate conductor and the self-aligned contact is formed withinthe second ILD thickness.
 5. The structure as recited in claim 1,wherein the gate spacer formed on the other side remains to permitcontact between the self-aligned contact and the gate contact and toprevent contact between the trench contact and the gate conductor. 6.The structure as recited in claim 1, wherein the etch stop layer portionincludes a high-k dielectric material.
 7. The structure as recited inclaim 1, wherein the structure is formed in the active area to reducedevice area.